Monday 2 September 2019

Amiga to BeagleBone Black


 


Amiga 500 Zorro to BeagleBone Black

My Ramblings...

These are my thoughts on how to get an interface from an Amiga500 to a Beaglebone. The diagrams may not work at all, but they help me visualise the problems of interfacing. 


There are many challenges, the BBB has got limited PRU high speed IO lines - so I have opted to multiplex them. Additionally, BBB runs at 3v3 - and the Amiga is 5V; there will be many level converters but I am keeping it brief for now.

The Multiplex - Address Lines

For the one port, bytes are sampled in 3 clocks. This is typically with the ADDRESS SELECT line becomes VALID. This will signal the PRU to sample the values and check for an address in the most significant byte. 
I am trying to avoid a CPLD, but if needed I will offload the Address decode to one if I cant get it to run fast enough.

I should be able to latch all the addresses within 60nSeconds using just the PRU

Amiga 500 Main Clock (PAL variety)

 

Prototyping Board (Zorro connector) - with BBB attached

 I managed to source a connector - and soldered to a Prototyping board. Bending the pins on the connector to make it right angled was a tiresome task.. and getting all the pins though the holes was a challenge when all the legs have a mind of their own


 

The DATA bus buffers

As the BBB does not have fast switching of INPUT and OUTPUT, a multiplex was chosen so that all INPUTS are on one set of pins.. and outputs on another.

All reads are muxed to PRU0 and Writes are to PRU1. 74HCT573 latches are used to put lock the data on the bus in preparation for reading from the master - and after read the pins are set to high impedance as to not mess with the data in the case of a read. 


  Address and Some MUXing action..

Amiga timing 

From the charts, it looks like 300nSeconds is average... but 200nSeconds was seen on my scope? Either way.. I was aiming for 200nSeconds as a maximum